1. Field of the Invention
This invention relates to an electronic material, its manufacturing method, dielectric capacitor, non-volatile memory and semiconductor device.
2. Description of the Related Art
Ferroelectric memory is non-volatile memory permitting high-speed rewriting utilizing high-speed polarization inversion and residual polarization of a ferroelectric film. An example of conventional ferroelectric memory is shown in FIG. 1.
As shown in FIG. 1, in the conventional ferroelectric memory, a field insulating film 102 is selectively formed on the surface of a p-type Si substrate 101 to separate devices. A gate insulating film 103 is formed on the surface of an active region surrounded by the field insulating film 102. Reference symbol WL denotes a word line. An n.sup.+ -type source region 104 and an n.sup.+ -type drain region 104 are formed in a p-type Si substrate 101 at opposite sides of the word line WL. The word line WL, source region 104 and drain region 105 form a transistor Q.
Numeral 106 denotes an inter-layer insulating film. Films are stacked sequentially on the inter-layer insulating film 106 above the field insulating film 102 via a Ti film 107, 30 nm thick, for example, as a bonding layer, which are, namely, a Pt film 108 with a thickness about 200 nm as the lower electrode, a ferroelectric film 109 made of Pb(Zr, Ti)O.sub.3 (PZT) or SrBi.sub.2 Ta.sub.2 O.sub.9 (SBT) with a thickness about 200 nm, and a Pt film 110 with a thickness about 200 nm as the upper electrode. The Pt film 108, ferroelectric film 109 and Pt film 110 form a capacitor C. The transistor Q and the capacitor C form a memory cell.
Numeral 111 denotes an inter-layer insulating film. A contact hole 112 is made to pass through the inter-layer insulating film 106 and the inter-layer insulating film 111 above the source region 104. Another contact hole 113 is made to pass through the inter-layer insulating film 111 above one end portion of the Pt film 108. Another contact hole 114 is made to extend through the inter-layer insulating film 111 above the Pt film 110. The source region 104 and the lower electrode of the capacitor C, namely, Pt film 108, are connected by a wiring line 115 through the contact holes 112 and 113. A wiring line 116 is connected to the upper electrode of the capacitor C, namely, Pt film 110 through the contact hole 114. Numeral 117 denotes a passivation film.
In the conventional ferroelectric memory shown in FIG. 1, the transistor Q and the capacitor C are arranged in a horizontal direction (in parallel to the substrate surface). However, in order to increase the information recording density of the ferroelectric memory, it is necessary to arrange the transistor Q and the capacitor C in a vertical direction (normal to the substrate surface). FIG. 2 shows an example employing such a vertical arrangement. In FIG. 2, elements identical to those of FIG. 1 are labelled with common numerals.
In FIG. 2, numerals WL1 through WL4 denote word lines, and 118 denotes an inter-layer insulating film. A contact hole 119 is made to pass through the inter-layer insulating film 118 above the drain region 105, and a bit line BL is connected to the drain region 105 of the transistor Q through the contact hole 119. Numerals 120 and 121 denote inter-layer insulating films. Another contact hole 122 is made through the inter-layer insulating film 121 above the source region 104, and a poly-crystalline Si plug 123 is embedded in the contact hole 122. The source region 104 of the transistor Q and the Pt film 108 used as the lower electrode of the capacitor C are electrically connected by the poly-crystalline Si plug 123.
To form the ferroelectric film 109, it is usually necessary to anneal it in an oxygen atmosphere at a high temperature about 600 to 800.degree. C. for its crystallization. There occurs the problem that Si in the poly-crystalline Si plug 123 thermally diffuses into the Pt film 108 as the lower electrode of the capacitor C, which results in Si being oxidized along the surface of the Pt film 108 to make it electrically non-conductive or low-conductive, and in Si diffusing further into the ferroelectric film 109 to significantly deteriorate the characteristics of the capacitor C.
A report states that, when the material of the ferroelectric film 109 is PZT whose calcination temperature is around 600.degree. C., a nitride compound film, such as TiN, can be used as a layer for preventing diffusion of Si (Extended Abstracts of Spring Meeting, 1995 of The Japan Society of Applied Physics, 30p-D-20, 30p-D-10). However, considering that a nitride compound film is oxidized and loses the electric conductivity when annealed in an oxygen atmosphere at a high temperature, if a higher temperature is applied during annealing by introducing sufficient oxygen into the annealing atmosphere for the purpose of improving the ferroelectric characteristics of the ferroelectric film 109, then it causes surface coarseness by oxidization or an increase in electric resistance.
On the other hand, when SBT, believed to be more excellent in fatigue characteristics than PZT, is used as the material of the ferroelectric film 109, the annealing temperature for obtaining acceptable ferroelectric characteristics is as higher as 800.degree. C. than PZT. Therefore, when SBT is used as the material of the ferroelectric film 109, the diffusion preventing layer made of the nitride compound mentioned above has an insufficient heat resistivity, and cannot be used.
Heretofore, no capacitor structure of a stacked type using SBT as the material of the ferroelectric film 109 has been reported, and it has been believed difficult to realize high-integrated non-volatile memory using such capacitors.
Additionally, the above-indicated problems may occur also when a W plug is used instead of poly-crystalline Si plug.
On the other hand, there is a ultra-high integrated semiconductor integrated circuit device having a multi-layered wiring structure whose minimum patterning size is 0.50 to 0.35 .mu.m as shown in FIG. 3 (for example, Nikkei Microdevice, 1994 July, pp. 50-57 and Nikkei Microdevice, 1995 September, pp. 70-77).
As shown in FIG. 3, this conventional semiconductor integrated circuit device has formed p-wells 202 and n-wells 203 in an n-type Si substrate 201. The n-type Si substrate 201 has a recess 204 in the region to be used as the device separating region along its surface, and a field insulating film 205 made of SiO.sub.2 is embedded in the recess 204. Along the surface of the active region surrounded by the field insulating film 205, a gate insulating film 206 made of SiO.sub.2 is formed. Numeral 207 denotes a poly-crystalline Si film, and 208 denotes a metal silicide film such as WSi.sub.x film. These poly-crystalline Si film 207 and metal silicide film 208 form a polycide-structured gate electrode. Formed on side walls of these poly-crystalline Si film 207 and metal silicide film 208 is a side wall spacer 209 made of SiO.sub.2. In each n-well 203, p.sup.+ -type diffusion layers 210 and 211 used as the source region or drain region are formed in self alignment with the gate electrode composed of the poly-crystalline Si film 207 and the metal silicide film 208. These gate electrode and diffusion layers 210, 211 form a p-channel MOS transistor. Similarly, an n-channel MOS transistor is formed in each p-well 202. Numerals 212 and 213 denote n.sup.+ -type diffusion layers used as the source region or drain region of the n-channel MOS transistor.
An inter-layer insulating film 214 is formed to cover the p-channel MOS transistor and the n-channel MOS transistor. The inter-layer insulating film 214 has formed via holes 215 and 216 at the portion aligned with the diffusion layer 211 of the p-channel MOS transistor and the portion aligned with the gate electrode on the field insulating film 205. W plugs 219 are embedded in the via holes 215 and 216 via Ti films 217 and TiN films 218.
An Al--Cu alloy wiring 222 overlie the via holes 215, 216 via a Ti film 220 and a TiN film 221, and a TiN film 223 is formed on the Al--Cu alloy wiring 222. Numeral 224 denotes an inter-layer insulating film. The inter-layer insulating film 224 has formed via holes 225, 226 in locations above the Al--Cu alloy wiring 222. Embedded in the via holes 225, 226 are W plugs 229 via a Ti film 227 and a TiN film 228.
An Al--Cu alloy wiring 232 overlies the via holes 225, 226 via a Ti film 230 and a TiN film 231, and a TiN film 233 is formed thereon.
In the semiconductor integrated circuit device shown in FIG. 3, the TiN film 217 (typically 5 to 50 nm thick) formed on the diffusion layer 211 in the location for the via hole 215 is used mainly for good electric connection of the W plug 219 with the diffusion layer 211 and for improvement of its adhesivity to the underlying layer, because, since the surface of the diffusion layer 211 is chemically active, and when it is exposed to moisture or atmospheric air, a thin SiO.sub.x film about 0.5 to 5 nm is formed along the surface in a very short time (presumably less than two to three minutes), and degrades the electric connection and the adhesivity to the diffusion layer 211. In contrast, when the Ti film 217 is formed on the diffusion layer 211, the Ti film 217 chemical reacts on the SiO.sub.x film on the surface of the diffusion layer 211, and results in improving the electric connection and the mechanical adhesivity.
However, when the W plug 219 (typically 50 to 700 nm thick) is formed on the diffusion layer 211 via the TiN film 217, chemical reaction occurs between Si in the diffusion layer 211 and the W plug 219 to form WSi.sub.x during annealing for making the W plug 219 (typically at 300 to 500.degree. C.) or later annealing (typically at 350 to 450.degree. C.). As a result, transportation of substance occurs (mainly, Si moves from the diffusion layer 211 into the W plug 219), and makes a gap between the diffusion layer 211 and the W plug 219, which causes insufficient electric connection there. On account of this problem, in order to prevent chemical reaction between the diffusion layer 211 and the W plug 219, the TiN film 218 (typically 5 to 50 nm thick) is inserted between the Ti film 217 and the W plug 219. Therefore, the TiN film 218 is called a barrier metal. In addition to the TiN film, also a TiON film is an example of the barrier metal.
The TiN film 220 formed on the W plug 219 is used for good electric connection and mechanical connection between the W plug 219 and the Al--Cu alloy wiring 222. The TiN film 221 on the Ti film 220 is used for reducing transportation of substances between the W plug 219 and the Al--Cu alloy wiring 222 and their chemical reaction. This is so for the Ti film 230 and the TiN film 231 formed on the W plugs 229 at locations of the via holes 225, 226.
However, upon manufacturing the semiconductor integrated circuit device mentioned above, if the W plug 219 is formed via the TiN film 217 and the TiN film 218, the maximum processing temperature in later steps is limited below the heat-resistant temperature of the TiN film 218. Since the heat resistant temperature of the TiN film 218 is as low as 500.degree. C. (when made by sputtering) to 650.degree. C. (when made by CVD), there is little room for choice regarding a process temperature and time. This problem occurs also when a Si plug or Al plug is used in lieu of the W plug 219.
As reviewed above, it has been difficult to use SBT requiring high-temperature annealing as the material of the ferroelectric film 109 of the capacitor C in a device, such as the conventional ferroelectric memory shown in FIG. 2, using vertical arrangement of the transistor Q and the capacitor C and connecting the lower electrode of the capacitor C, namely the Pt film 108, to the source region 104 of the transistor Q by the poly-crystalline Si plug 123 or W plug.
Additionally, in the conventional semiconductor integrated circuit device shown in FIG. 3, there has been little room for choice regarding the process temperature and time in later steps after formation of the W plug 219.